姜书艳数字逻辑设计及应用17.ppt

1 1Chapter 7 Sequential Logic Design Chapter 7 Sequential Logic Design PrinciplesPrinciples(时序逻辑设计原理时序逻辑设计原理 )Latches and Flip-Flops (锁存器和触发器锁存器和触发器)Clocked Synchronous State-Machine Analysis (同步时序分析同步时序分析)Clocked Synchronous State-Machine Design (同步时序设计同步时序设计)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)2 2IntroductionIntroductionCombinational circuitOutputs depend solely on the present combination of the circuit inputs valuesDigitalSystemb=0F=0DigitalSystemif b=0,then F=0if b=1,then F=1b=1F=1(a)DigitalSystemb=0F=0DigitalSystemb=1F=1DigitalSystemb=0F=1Cannot determine value ofF solely from presentinput value(b)Vs.sequential circuit:Has“memory”that impacts outputs too3 3Basic Concepts(Basic Concepts(基本概念基本概念)Logic Circuits are Classified into Two Types(逻辑电路分为两大类逻辑电路分为两大类)：Combinational Logic Circuit （组合逻辑电路组合逻辑电路）Sequential Logic Circuit （时序逻辑电路时序逻辑电路）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)4 4Basic Concepts(Basic Concepts(基本概念基本概念)Combinational Logic Circuit （组合逻辑电路组合逻辑电路）Outputs Depend Only on its Current Inputs.(任何时刻的输出仅取决与当时的输入任何时刻的输出仅取决与当时的输入)Character of Circuit:No Feedback Circuit,No Memory Device(电路特点：无反馈回路、无记忆元件电路特点：无反馈回路、无记忆元件)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)5 5Basic Concepts(Basic Concepts(基本概念基本概念)Sequential Logic Circuit （时序逻辑电路时序逻辑电路）Outputs Depend Not Only on its Current Inputs,But also on the Past Sequence of Inputs.(任一时刻的输出不仅取决与当时的输入，任一时刻的输出不仅取决与当时的输入，还取决于过去的输入序列还取决于过去的输入序列)Character of Circuit:Have Feedback Circuit,Have Memory Device(电路特点：有电路特点：有反馈回路反馈回路、有、有记忆元件记忆元件)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)6 6Basic Concepts(Basic Concepts(基本概念基本概念)Sequential Logic Circuit （时序逻辑电路时序逻辑电路）Finite-State Machine:Have Finite States.(有限状态机：有有限个状态。）有限状态机：有有限个状态。）A Clock Signal is Active High if state changes occur at the clock Rising Edge or when the clock is High,and Active Low in the complementary case.(时钟信号时钟信号高电平有效是指在时钟信号的高电平有效是指在时钟信号的上升沿上升沿或时或时钟的钟的高电平期间高电平期间发生变化。）发生变化。）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)7 7Basic Concepts(Basic Concepts(基本概念基本概念)Sequential Logic Circuit （时序逻辑电路时序逻辑电路）Clock Period:The Time between Successive transitions in the same direction.(时钟周期：两次连续同向转换之间的时间。）时钟周期：两次连续同向转换之间的时间。）Clock Frequency:The Reciprocal of the Clock Period(时钟频率：时钟频率：时钟周期的倒数。）时钟周期的倒数。）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 7-18 8Basic Concepts(Basic Concepts(基本概念基本概念)Sequential Logic Circuit （时序逻辑电路时序逻辑电路）Clock Tick:The First Edge of Pulse in a clock period or sometimes the period itself.(时钟触发沿：时钟周期内的第一个脉冲边沿，或时时钟触发沿：时钟周期内的第一个脉冲边沿，或时钟本身。）钟本身。）Duty Cycle:The Percentage of time that the clock signal is at its asserted level.(占空比：占空比：时钟信号有效时间与时钟周期的百分比。）时钟信号有效时间与时钟周期的百分比。）Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)Figure 7-19 9思考：能否只用一片思考：能否只用一片1 1位位全加器进行串行加法？全加器进行串行加法？C1S0X0 Y0C0X YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串串行行加加法法器器C1C2X YCI COSC2S1X1 Y1C1反馈反馈利用反馈和时钟控制利用反馈和时钟控制C3S2X2 Y2C2Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1010暂存暂存X YCI COSCi+1SiXi YiCiX YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串串行行加加法法器器C1C1时钟控制时钟控制需要具有需要具有记忆记忆功能功能的逻辑单元，能够的逻辑单元，能够暂存运算结果。暂存运算结果。利用利用反馈反馈和时钟控制和时钟控制Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)11 117.1 Bistable Elements(7.1 Bistable Elements(双稳态元件双稳态元件)QQ_L1100QQ_LIt has Two Stable State:Q=1(HIGH)and Q=0(LOW)(电路有两种电路有两种稳定状态稳定状态：Q=1(1态态)和和 Q=0(0态态)Bistable Circuit（双稳电路）（双稳电路）0011Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)12127.1 Bistable Elements(7.1 Bistable Elements(双稳态元件双稳态元件)QQ_L1100QQ_LWhen Power is first Applied to the circuit,it Randomly Comes up in One State or the Other and Stays there Forever.(只要一接电源，电路就随机出现两种状态中的一种，只要一接电源，电路就随机出现两种状态中的一种，并永久地保持这一状态。并永久地保持这一状态。)0011Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1313Vin1Vout1Vin2Vout2Vout2Vin2=Vin2=Vout2稳态稳态 stable亚稳态亚稳态 metastableQQ_LVin1 Vout1Vin2 Vout2Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1414Metastable BehaviorMetastable Behavior(亚稳态特性亚稳态特性)Random Noise will tend to Drive a circuit that is Operating at the Metastable Point toward one of the Stable operating point.(随机噪声会驱动工作于亚稳态点的电路转移到一个随机噪声会驱动工作于亚稳态点的电路转移到一个稳态的工作点上去稳态的工作点上去)QQ_LDigital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)1515所有的时序电路对所有的时序电路对亚稳态都是敏感的亚稳态都是敏感的Metastable BehaviorMetastable Behavior(亚稳态特性亚稳态特性)稳态稳态稳态稳态亚稳态亚稳态Apply a definite Pulse Width from a Stable state to the Other.(从一个从一个“稳态稳态”转换到另一个转换到另一个“稳态稳态”需加一定宽度的脉冲（足够的驱动）需加一定宽度的脉冲（足够的驱动）)Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)16167.2 Latches and Flip-Flops7.2 Latches and Flip-Flops(锁存器与触发器锁存器与触发器)The Basic Building Blocks of most Sequential Circuits.(大多数时序电路的基本构件大多数时序电路的基本构件)LatchesLatches（锁存器）（锁存器）根据输入，直接改变其输出（无使能端）根据输入，直接改变其输出（无使能端）有使能端时，在使能信号的有效电平之内都可根有使能端时，在使能信号的有效电平之内都可根据输入直接改变其输出状态据输入直接改变其输出状态Digital Logic Design and Application(数字逻辑设计及应用数字逻辑设计及应用)17177.2 Latches and Flip-Flops7.2 Latches and Flip-Flops(锁存器与触发器锁存器与触发器)The Basic Building Blocks of most Sequential Circuits.(大